Digital Logic Simulator

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SCHEMATIC VIEW · Scroll canvas to pan

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Using Digital Logic Simulator

Choose a sample or place components, connect compatible pins and adjust inputs. Recalculate combinational outputs or pulse the clock to explore memory. Inspect waveforms or a supported truth table and download JSON to keep an editable backup.

States are ideal 0, 1 or unknown X, without physical propagation delay or accurate hardware timing. Auto clock playback is approximate; combinational truth tables support at most eight switches. Structural changes clear waveform history, which is not saved in JSON. Browser storage and multi-tab conflict handling are best effort.

Choose an editable circuit, diagram or logic table

Project JSON: preserve supported components and wiring.

SVG or PNG: share the visual logic circuit.

CSV: export supported signal history for review.

Waveforms: inspect current logical history, separately from the editable project backup.

Practice: compare two switch inputs

Open a simple combinational example or connect two switches to a supported gate.

Change the inputs and inspect the resulting logical states.

Use a supported truth table, then save JSON before changing the circuit structure.

This is an authored logic exercise, not a propagation-delay test or a hardware waveform capture.

Digital logic questions

Does the waveform show accurate physical gate timing?

No. States are ideal 0, 1 or unknown X, with supported rising-edge updates. Physical propagation delay and accurate real-time hardware timing are not modeled.

Why are a large truth table or old waveforms unavailable?

Combinational truth tables are bounded to eight switches. Structural changes clear waveform history, which is not saved in JSON. Keep supported CSV output separately when you need it.

Signal waveform

From basic gates to stateful circuits.